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? semiconductor components industries, llc, 2017 may, 2017 ? rev. 1 1 publication order number: ncl30073/d ncl30073 current-mode pwm controller for led application the ncl30073 is a highly integrated pwm controller capable of delivering a rugged and high performance led converter in a tiny tsop?6 package. with a supply range up to 24 v, the controller hosts a 65 khz switching circuitry operated in peak current mode control. when the voltage on fb pin decreases, the controller enters skip cycle while limiting the peak current. over power protection (opp) is a difficult exercise especially when no?load standby requirements drive the converter specifications. the on proprietary integrated opp lets you harness the maximum delivered power without affecting your standby performance simply via two external resistors. an over voltage protection is also combined on the same pin but also on the v cc line. they offer an efficient protection in case of adverse open loop operation. finally, a timer?based short?circuit protection offers the best protection scheme, letting you precisely select the protection trip point without caring of a loose coupling between the auxiliary and the power windings. features ? fixed?frequency 65 khz current?mode control operation ? internal and adjustable over power protection (opp) circuit ? internal ramp compensation ? internally fixed 4 ms soft?start ? 115 ms timer?based auto?recovery short?circuit protection ? protection ? autorecovery ? ovp by v cc ? oip ? otp ? foldback ? short circuit ? up to 24 v v cc operation ? extremely low no?load standby power ? isolated and non?isolated outputs ? good regulation ? 5% ? high power factor > 0.9 ? single winding inductor ? low parts count ? eps 2.0 compliant ? pb?free devices ? +300 ma/ ?500 ma source/sink drive capability typical application ? dimmable retrofit and low power fixture led applications ? phase cut dimmer compatible ? le or te types ? multiple topology support ? buck ? buck boost ? flyback www. onsemi.com ordering information device package shipping ? NCL30073SN065T1G tsop?6 (pb?free) 3000 / tape & reel tsop?6 case 318g?02 marking diagram ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. (note: microdot may be in either location) pin connections 1 73a = specific device code a =assembly location y = year w = work week = pb?free package 73aayw 1 opp fb cs gnd drv vcc tsop?6 (top view)
ncl30073 www. onsemi.com 2 typical application schematic figure 1. typical non?isolated (buck?boost) application figure 2. typical isolated (flyback) application example table 1. pin function description pin # pin name function pin description 1 opp adjust the over power protection a resistive divider from the auxiliary winding to this pin sets the opp compensation level. when brought above 3 v, the part enters auto?recovery mode. 2 fb feedback pin a voltage variation on this pin will allow regulation. 3 cs current sense + slope compensation this pin monitors the primary peak current but also offers a means to introduce slope compensation. 4 gnd the controller ground. 5 drv driver output the driver output to an external mosfet gate. 6 v cc supplies the controller ? protects the ic this pin is connected to an external auxiliary voltage. when the v cc exceeds a certain level, the part enters an auto?recovery hiccup mode.
ncl30073 www. onsemi.com 3 internal circuit architecture figure 3. internal circuit architecture 65 khz oscillator clamp drv v cc and logic management vcc + v ovp gnd opp + v l atch up counter to 4 cs fb v fb(open ) r eq k ratio r ramp peak current freeze soft-start + v limit +v opp v opp up counter to 8 _ + + _ + _ rst t latch(del ) t latch(blank ) t ovp (del) + _ + v skip s r q q d max leb v limit + _ + fault timer ocp fault rst rst drv pulse v opp drv pulse r s q q error flag drv pulse drv pulse auto-recovery management ovp/otp v cc(ovp ) ic stop drv stop v cc(ovp ) v cc (min) ic start ic stop ic reset ocp fault auto-recovery mode drv stop auto-recovery mode internal supply ic in regulation ovp /otp
ncl30073 www. onsemi.com 4 table 2. maximum ratings table symbol rating value units v cc power supply voltage, vcc pin, continuous voltage ?0.3 to 35 v v drv(tran) maximum drv pin voltage when drv in h state, transient voltage (note 1) ?0.3 to v cc + 0.3 v v cs , v fb , v opp maximum voltage on low power pins cs, fb and opp (note 2) ?0.3 to 5.5 v v opp(tran) maximum negative transient voltage on opp pin (note 2) ?1 v i source,max maximum sourced current, pulsed width < 800 ns 0.6 a i sink,max maximum sinked current, pulse width < 800 ns 1.0 a i opp maximum injected negative current into the opp pin (pin 1) ?2 ma r j?a thermal resistance junction?to?air 360 c/w t j,max maximum junction temperature 150 c storage temperature range ?60 to +150 c hbm human body model esd capability per jedec jesd22?a114f (all pins) 4 kv cdm charged?device model esd capability per jedec jesd22?c101e 750 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the transient voltage is a voltage spike injected to drv pin being in high state. maximum transient duration is 100 ns. 2. see the figure 4 for detailed specification of transient voltage. 3. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. figure 4. negative pulse for opp pin during on?time and positive pulse for all low power pins 500 ns ?1 v 0 v v opp must stay between 0 v and ?0.3 v for a linear opp operation on?time ? ? t soa max dc voltage max transient voltage cycle?by?cycle max current during overshoot can?t exceed 3 ma 500 ns 7.5 v 5.5 v 0 v v opp,max = ?0.75 v, t j = ?25 c v opp,max = ?0.65 v, t j = 25 c v opp,max = ?0.3 v, t j = 125 c ? worst case v opp,max v opp v opp (t) v opp v fb v cs t
ncl30073 www. onsemi.com 5 table 3. electrical characteristics for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 12 v unless otherwise noted. symbol rating pin min typ max units supply section v cc(on) v cc increasing level at which driving pulses are authorized 6 16 18 20 v v cc(min) v cc decreasing level at which driving pulses are stopped 6 8.3 8.9 9.5 v v cc(hyst) hysteresis v cc(on) ? v cc(min) 6 7.7 ? ? v v cc(reset) auto?recovery state reset voltage 6 ? 8.6 ? v v cc(reset_hyst) defined hysteresis between minimum and reset voltage v cc(min) ? v cc(reset) 6 0.15 0.30 0.45 v i cc1 start?up current (v cc(on) ? 100 mv) 6 ? 6 10 a i cc2 internal ic consumption with v fb = 3.2 v, f sw = 65 khz and c l = 0 nf 6 ? 1.0 1.4 ma i cc3 internal ic consumption with v fb = 3.2 v, f sw = 65 khz and c l = 1 nf 6 ? 1.8 2.7 ma i cc(no?load) internal consumption in skip mode ? non switching, v fb = 0 v 6 ? 300 ? a i cc(fault) internal consumption in fault mode ? during going?down v cc cycle, v fb = 4 v 6 0.6 0.9 1.2 ma i cc(standby) internal ic consumption in skip mode for 65 khz version (v cc = 14 v, driving a typical 7 a / 600 v mosfet, includes fb pin current) ? (note 5) 6 ? 420 ? a drive output t r output voltage rise?time @ c l = 1 nf, 10?90% of output signal 5 ? 25 ? ns t f output voltage fall?time @ c l = 1 nf, 10?90% of output signal 5 ? 30 ? ns r oh source resistance, v cc = 12 v, i drv = 100 ma 5 ? 28 ? r ol sink resistance, v cc = 12 v, i drv = 100 ma 5 ? 7 ? i source peak source current, v gs = 0 v (note 4) 5 ? 300 ? ma i sink peak sink current, v gs = 12 v (note 4) 5 ? 500 ? ma v drv(low) drv pin level at v cc = v cc(min) + 100 mv with a 33 k resistor to gnd 5 8 ? ? v v drv(high) drv pin level at v cc = v ovp ? 100 mv (drv unloaded) 5 10 12 14 v current comparator v limit maximum internal current set point (pin 1 grounded) t j = 25 c t j = ?40 c to 125 c 3 0.744 0.720 0.810 0.810 0.856 0.880 v v cs(freeze) internal peak current setpoint freeze ( 31% of v limit ) 3 ? 260 ? mv t del propagation delay from cs pin to drv output 3 ? 35 80 ns t leb leading edge blanking duration 3 ? 270 ? ns t ss internal soft?start duration activated upon startup or auto?recovery 3 ? 4.1 ? ms i opps set point decrease for pin 1 grounded 1 ? 0 ? % i oppo set point decrease for pin 1 biased to ?250 mv (note 4) 1 ? 31.3 ? % i oopv voltage set point for pin 1 biased to ?250 mv t j = 25 c t j = ?40 c to 125 c 1 0.51 0.50 0.55 0.55 0.60 0.62 v internal oscillator f osc(nom) oscillation frequency t j = 25 c t j = ?40 c to 125 c ? 63.0 61.0 65.5 65.5 67.0 69.0 khz d max maximum duty?ratio ? 76 80 84 %
ncl30073 www. onsemi.com 6 table 3. electrical characteristics for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, v cc = 12 v unless otherwise noted. symbol units max typ min pin rating feedback section r eq internal equivalent feedback resistance 2 ? 29 ? k k ratio fb pin to current set point division ratio ? ? 4 ? ? v fb(freeze) feedback voltage below which the peak current is frozen 2 ? 1 ? v v fb(limit) feedback voltage corresponding with maximum internal current set point 2 ? 3.2 ? v v fb(open) internal pull?up voltage on fb pin 2 ? 4 ? v skip section v skip skip?cycle level voltage on the feedback pin ? ? 0.8 ? v v skip(hyst) hysteresis on the skip comparator (note 4) ? ? 50 ? mv internal slope compensation v ramp internal ramp level @ 25 c (note 6) 3 ? 2.5 ? v r ramp internal ramp resistance to cs pin 3 ? 20 ? k protections v (latch) fault level input on opp pin 1 2.85 3.0 3.15 v t latch (blank) blanking time after drive output turn off 1 ? 1 ? s t latch (count) number of clock cycles before fault is confirmed 1 ? 4 ? t latch (del) ovp/otp delay time constant before fault is confirmed 1 ? 600 ? ns t fault internal auto?recovery fault timer duration ? 100 115 130 ms v ovp over voltage protection on the vcc pin 6 24.0 25.5 27.0 v t ovp(del) delay time constant before ovp on vcc is confirmed 6 ? 20 ? s 4. guaranteed by design. 5. application parameter for information only. 6. 1 m resistor is connected from pin 3 to the ground for the measurement.
ncl30073 www. onsemi.com 7 figure 5. figure 6. figure 7. figure 8. figure 9. figure 10.
ncl30073 www. onsemi.com 8 figure 11. figure 12. figure 13. figure 14. figure 15. figure 16.
ncl30073 www. onsemi.com 9 figure 17. figure 18. figure 19. figure 20. figure 21. figure 22.
ncl30073 www. onsemi.com 10 figure 23. figure 24. figure 25. figure 26. figure 27. figure 28.
ncl30073 www. onsemi.com 11 figure 29. figure 30. figure 31. figure 32. figure 33. figure 34.
ncl30073 www. onsemi.com 12 figure 35. figure 36. figure 37.
ncl30073 www. onsemi.com 13 application information introduction ncl30073 implements a standard current mode architecture where the switch?off event is dictated by the peak current set point. this component represents the ideal candidate for led applications. the ncl30073 packs all the necessary components normally needed in today modern led converter designs, bringing several enhancements such as a non?dissipative opp, ovp/otp implementation, short?circuit protection, improved consumption, robustness and esd capabilities. ? current?mode operation with internal slope compensation: implementing peak current mode control at a 65 khz switching frequency, the ncl30073 offers an internal slope compensation signal that can easily by summed up to the sensed current. sub harmonic oscillations can thus be fought via the inclusion of a simple resistor in series with the current?sense information. ? internal opp: by routing a portion of the negative voltage present during the on?time on the auxiliary winding to the dedicated opp pin (pin 1), the user has a simple and non?dissipative means to alter the maximum peak current set point as the bulk voltage increases. if the pin is grounded, no opp compensation occurs. if the pin receives a negative voltage, then a peak current is reduced down. ? low startup and standby current: reaching a low no?load standby power always represents a difficult exercise when the controller draws a significant amount of current during startup. ? skip capability: a continuous flow of pulses is not desired in all application. the controller monitors fb pin voltage and when it reaches a level of v skip , the controller enters skip?cycle mode, to reduce number of switching periods ? internal soft?start: a soft?start precludes the main power switch from being stressed upon start?up. the soft?start duration is internally fixed for time t ss and it is activated during new startup sequence or during recovering after auto?recovery hiccup mode. ? auto?recovery input: the controller includes an opp input (pin 1) that can be used to sense an over voltage or an over temperature event on the converter. if this pin is brought higher than the internal reference voltage v latch for four consecutive cycles, then the circuit enters into auto?recovery mode. ? auto?recovery ovp on v cc : an ovp protects the circuit against v cc runaways. if the fault is present at least for time t ovp(del) then the ovp is validated and the controller enters hiccup mode. when the v cc returns to a nominal level, the controller resumes operation. ? short?circuit protection: short?circuit and especially overload protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). in this controller, every time the internal maximum peak current limit v limit is activated (or less when opp is used), an error flag is asserted and a time period starts thanks to an internal timer. when the timer has elapsed while a fault is still present, the controller enters an auto?recovery mode. start?up sequence the ncl30073 star t?up voltage is made purposely high to permit large energy storage in a small v cc capacitor value. this helps operate with a small start?up current which, together with a small v cc capacitor, will not hamper the start?up time. to further reduce the standby power, the start?up current of the controller is extremely low, below 10 a. the start?up resistor can therefore be connected to the bulk capacitor or directly to the mains input voltage to further reduce the power dissipation.
ncl30073 www. onsemi.com 14 figure 38. the startup resistor can be connected to the input mains for further power dissipation reduction aux. winding + + + vcc input mains c bulk r start?up c vcc the first step starts with the calculation of the needed vcc capacitor which will supply the controller which it operates until the auxiliary winding takes it over . experience shows that this time t 1 can be between 5 and 20 ms. if we consider we need at least an ener gy reservoir for a t 1 time of 10 ms, the vcc capacitor must be larger than: c vcc i cc t 1 v cc(on) v cc(min) 1.6m 10m 18 8.9 1.7 f (eq. 1) let us select a 2.2 f capacitor at first and experiments in the laboratory will let us know if we were too optimistic for the time t 1 . the vcc capacitor being known, we can now evaluate the charging current we need to bring the v cc voltage from 0 v to the v cc(on) of the ic. this current has to be selected to ensure a start?up at the lowest mains (85 v rms ) to be less than 200 ms (acceptable time): i charge v cc(on) c vcc t start up 18 2.2 0.1 198 a (eq. 2) if we account for the 10 a (maximum) that will flow to the controller, then the total charging current delivered by the start?up resistor must be 208 a. if we connect the start?up network to the mains (half?wave connection then), we know that the average current flowing into this start?up resistor will be the smallest when v cc reaches the v cc(on) of the controller: i cvcc,min v ac,rms 2 v cc(on) r start up (eq. 3) to make sure this current is always greater than 346 a, then, the minimum value for r start?up can be extracted: r start up v ac,rms 2 v cc(on) i cvcc(min) 85 2 18 208 97 k (eq. 4) this calculation is purely theoretical, considering a constant charging current. in reality, the take over time can be shorter (or longer!) and it can lead to a reduction of the vcc capacitor. thus, a decrease in charging current and an increase of the start?up resistor can be experimentally tested, for the benefit of standby power. laboratory experiments on the prototype are thus mandatory to fine tune the converter. if we chose the 92 k resistor as suggested by eq.4 , the dissipated power at high line amounts to: p r start up,max v ac,peak 2 4 r start up (230 2 ) 2 4 92k 287 mw (eq. 5) now that the first vcc capacitor has been selected, we must ensure that the self?supply does not disappear when in no?load conditions. in this mode, the skip?cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the vcc capacitor. if this ripple is too large, chances exist to touch the v cc(min) and reset the controller into a new start?up sequence. a solution is to grow this capacitor but it will obviously be de trimental to the start?up time. the option offered in figure 38 elegantly solves this potential issue by adding an extra capacitor on the auxiliary winding. however, this component is separated from the vcc pin via a simple diode. you therefore have the ability to grow this capacitor as you need to ensure the self?supply of the controller without affecting the start?up time and standby power. internal over power protection there are several known ways to implement over power protection (opp), all suffering from particular problems. these problems range from the added consumption burden on the converter or the skip?cycle disturbance brought by the current?sense offset. a way to reduce the power capability at high line is to capitalize on the negative voltage
ncl30073 www. onsemi.com 15 swing present on the auxiliary diode anode. during the turn?on time, this point dips to ?n 2 v bulk , where n 2 being the turns ratio between the primary winding and the auxiliary winding. the negative plateau observed on figure 39 will have amplitude depending on the input voltage. the idea implemented in this chip is to sum a portion of this negative swing with the internal voltage reference v limit = 0.8 v. for instance, if the voltage swings down to ?150 mv during the on?time, then the internal peak current set point will be fixed to the value 0.8 v ? 0.150 v = 650 mv. the adopted principle appears in figure 40 and shows how the final peak current set point is constructed. let?s assume we need to reduce the peak current from 2.5 a at low line, to 2 a at high line. this corresponds to a 20% reduction or a set point voltage of 640 mv. to reach this level, then the negative voltage developed on the opp pin must reach: v opp 0.8 v limit v limit 0.64 0.8 160 mv (eq. 6) figure 39. the signal obtained on the auxiliary winding swings negative during the on?time 464u 472u 488u 496u time in seconds ?40.0 ?20.0 0 20.0 40.0 1 ? on?time 480u ?40.0 ?20.0 0 20.0 40.0 plot1 in volts 1 ? off?time n 1 (v out + v f ) n 2 v bulk figure 40. the opp circuitry affects the maximum peak current set point by summing a negative voltage to the internal voltage reference opp r oppl v cc r oppu aux. winding + i opp ref = 0.8v + v opp v limit = 0.8 v 7% + + _ driver reset cs r sense k1 k2 sum ref (v opp is negative ) this point will be adjusted to reduce the ?ref? at hi line to the desired level swings to: n 1 v out during t off ?n 2 v in during t on
ncl30073 www. onsemi.com 16 the opp pin is surrounded by zener diodes stacked to protect the pin against esd pulses. these diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. on the other side, negative injection into these diodes (or forward bias) can cause substrate injection which can lead to an erratic circuit behavior. to avoid this problem, the pin is internal clamped slightly below ?300 mv which means that if more current is injected before reaching the esd forward drop, then the maximum peak reduction is kept to 40%. if the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond ?2 ma. finally, please note that another comparator internally fixes the maximum peak current set point to value v limit even if the opp pin is adversely biased above 0 v. short?circuit protection in case of output short?circuit or if the led converter experiences a severe overloading situation, an internal error flag is raised and the fault timer starts countdown. if the uvlo has come (see figure 41 ? short?circuit case i.) or the error flag is asserted throughout the t fault time (see figure 41 ? short?circuit case ii.) ? i.e. the fault timer has elapsed, the driving pulses are stopped and the v cc falls down as the auxiliary voltage are missing. when the supply voltage v cc touches the v cc(min) level, the controller consumption is down to a few a and the v cc slowly builds up again thanks to the resistive startup network. when v cc reaches v cc(on) , the controller enter into start?up cycle. please note that soft?start is activated upon every re?start attempt. figure 41. an auto?recovery description t t t t error flag short?circuit case ii. error flag raised fault timer elapsed auto?recovery fault timer has elapsed short?circuit case i. error flag raised uvlo auto?recovery ss v cc (t) v cc(on) v cc(min) v drv (t) v cs (t) v limit fault timer has elapsed
ncl30073 www. onsemi.com 17 slope compensation the ncl30073 includes an internal slope compensation signal. this is the buffered oscillator clock delivered during the on?time only. its amplitude is around 2.5 v at the maximum duty ratio. slope compensation is a known means used to cure sub harmonic oscillations in ccm?operated current?mode converters. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty ratio greater than 50%. to lower the current loop gain, one usually injects between 50 and 100% of the primary inductance downslope. figure 42 depicts how the ramp is generated internally. please note that the ramp signal will be disconnected from the cs pin during the off?time. figure 42. inserting a resistor in series with the current sense information brings slope compensation and stabilizes the converter in ccm operation 0v 2.5 v + _ cs 20 k on time from fb driver reset r ramp r comp r sense t leb t sw d max in the ncl30073 controller, the oscillator ramp features a 2.5 v swing. if the clock operates at a 65 khz frequency, then the available oscillator slope corresponds to: s ramp v ramp,peak d max t sw 2.5 0.8 15 208 mv s (eq. 7) in a flyback design, let?s assume that our primary inductance l p is 770 h, and the smps delivers 19 v with a n p : n s ratio of 1:0.25. the off?time primary current slope s p is thus given by: s p (v out
v f ) n s n p l p (19
0.7) 4 770 102 ma s (eq. 8) given a sense resistor of 330 m , the above current ramp turns into a voltage ramp of the following amplitude: s sense s p r sense 102m 0.33 34 mv s (eq. 9) if we select 50% of the downslope as the required amount of slope compensation, then we shall inject a ramp whose slope is 17 mv/ s. our internal compensation being of 208 mv/ s, the divider ratio ( divratio ) between r comp and the internal r ramp = 20 k resistor is: divratio 0.5 s sense s ramp 0.082 (eq. 10) the series compensation resistor value is thus: r comp r ramp divratio 20k 0.082 1.64 k (eq. 11) a resistor of the calculated value will then be inserted from the sense resistor to the current sense pin. we recommend adding a small capacitor of 100 pf, from the current sense pin to the controller ground for an improved immunity to the noise. please make sure both components are located very close to the controller.
ncl30073 www. onsemi.com 18 protection pin the opp pin not only allows a reduction of the peak current set point in relationship to the line voltage, it also offers a means to enter the auto?recovery mode. the auto?recovery detection is made by observing the opp pin by a comparator featuring a v latch reference voltage. however, for noise reasons and in particular to avoid the leakage inductance contribution at turn off, a blanking delay t latch?blank is introduced before the output of the ovp comparator is checked. then, the ovp comparator output is validated only if its high?state duration lasts for a minimum time t latch?del . below this value, the event is ignored. then, a counter ensures that only 4 successive ovp events have occurred before actually auto?recovery mode is triggered. there are several possible implementations, depending on the needed precision and the parameters you want to control. the first and easiest solution is the additional resistive divider on top of the opp one. this solution is simple and inexpensive but requires the insertion of a diode to prevent disturbing the opp divider during the on?time. figure 43. auto?recovery of the controller and resuming operation t t t the ic is latched after the fault is confirmed for 4 consecutive drv cycles v latch (t) v latch v cc (t) v cc(on) v cc(min) v cc(reset) v drv (t) figure 44. a simple resistive divider brings the opp pin above 3 v in case of a v cc voltage runaway above 18 v opp + _ + 100 p ovp opp aux. winding + r ovp d 1 r oppu v cc v latch r oppl c 1
ncl30073 www. onsemi.com 19 first, calculate the opp network with the above equations. then, suppose we want to trigger auto?recovery of our controller when v out exceeds 25 v. on the auxiliary winding, the plateau reflects the output voltage by the turns ratio between the power and the auxiliary winding. in case of voltage runaway for 19 v output, the plateau will go up to: v aux,ovp v out n s n aux 25 0.18 0.25 18 v (eq. 12) since our ovp comparator trips at level v latch = 3 v, across the 1 k selected opp pull?down resistor, it implies a 3 ma current. from 3 v to go up to 18 v, we need an additional 15 v. under 3 ma and neglecting the series diode forward drop, it requires a series resistor of: r ovp v out v aux,ovp v latch v ovp r oppl 18 3 3 1k 5k (eq. 13) in nominal conditions, the plateau establishes to around 14 v. given the divide by 6 ratio, the opp pin will swing to 14/6 = 2.3 v during normal conditions, leaving 700 mv for the noise immunity. a 100 pf capacitor can be added to improve it and avoid erratic trips in presence of external surges. do not increase this capacitor too much otherwise the opp signal will be affected by the integrating time constant. a second solution for the ovp detection alone is to use a zener diode wired as recommended by figure 45. figure 45. a zener diode in series with a diode helps to improve the noise immunity of the system opp + _ + 22p ovp opp aux. winding + 15 v r oppu d 1 c 1 r oppl v latch v cc in this case, to still trip at 18 v level, we have selected a 15 v zener diode. in nominal conditions, the voltage on the opp pin is almost 0 v during the off?time as the zener is fully blocked. this technique clearly improves the noise immunity of the system compared to that obtained from a resistive string as in figure 44. please note the reduction of the capacitor on the opp pin to 10?22 pf. this is because of the potential spike going through the zener parasitic capacitor and the possible auxiliary level shortly exceeding its breakdown voltage during the leakage inductance reset period (hence the internal blanking delay t latch?blank at turn off). this spike despite its very short time is energetic enough to charge the added capacitor c 1 and given the time constant, could make it discharge slower, potentially disturbing the blanking circuit. when implementing the zener option, it is important to carefully observe the opp pin voltage (short probe connections!) and check that enough margin exists to that respect.
ncl30073 www. onsemi.com 20 over temperature protection in a lot of designs, the converter must be protected against thermal runaways, e.g. when the temperature inside the converter box increases a certain value. figure 46 shows how to implement a simple otp using an external ntc and a series diode. the principle remains the same: make sure the opp network is not bothered by the additional ntc hence the presence of this diode. figure 46. the internal circuitry hooked to opp pin can be used to implement over temperature protection (otp) opp + _ + ovp opp aux. winding + ntc r oppu d 1 r oppl v latch v cc when the ntc resistor will diminish as the temperature increases, the voltage on the opp pin during the of f?time will slowly increase and, once it passes v latch level for 4 consecutive clock cycles, the controller will enter auto?recovery mode. we have found that the plateau voltage on the auxiliary diode was 14 v in nominal conditions. we have selected an ntc which offers a 470 k resistance at 25 c and drops to 8.8 k at 110 c. if our auxiliary winding plateau is 14 v and we consider a 0.7 v forward drop for the diode, then the voltage across the ntc in fault mode must be: v ntc v aux v latch v f 14 3 0.7 10.3 v (eq. 14) based on the 8.8 k ntc resistor at 110 c, the current inside the device must be: i ntc v ntc r ntc(110) 10.3 8.8k 1.2 ma (eq. 15) as such, the bottom resistor r oppl , can easily be calculated: r oppl v latch i ntc 2.5 k (eq. 16) now the pull down opp resistor is known, we can calculate the upper resistor value r oppu to adjust the power limit at the chosen output power level. suppose we need a 200 mv decrease from the v limit setpoint and the on?time swing on the auxiliary anode is ?67.5 v, then we need to drop over r oppu a voltage of: v r oppu v aux v opp ?67.5
0.2 ?67.3 v (eq. 17) the current circulating the pull down resistor r oppl in this condition will be: i r oppl v opp r oppl ?0.2 2.5k ?80 a (eq. 18) the r oppu value is therefore easily derived: r oppu v r oppu i r oppu ?67.3 ?80 841 k (eq. 19)
ncl30073 www. onsemi.com 21 combining ovp and otp the otp and zener?based ovp can be combined together as illustrated by figure 47. in nominal v cc /output conditions, when the zener is not activated, the ntc can drive the opp pin and trigger the protection in case of a fault. on the contrary, in nominal temperature conditions, if the loop is broken, the voltage runaway will be detected and acknowledged by the controller. in case the opp pin is not used for either opp or ovp, it can simply be grounded. figure 47. with the ntc back in place, the circuit nicely combines ovp, otp and opp on the same pin opp + _ + ovp opp aux. winding + ntc 15 v r oppu d 1 r oppl v latch v cc filtering the spikes the auxiliary winding is the seat of spikes that can couple to the opp pin via the parasitic capacitances exhibited by the zener diode and the series diode. to prevent an adverse triggering of the over voltage protection circuitry, we recommend the installation of a small rc filter before the detection network as illustrated by figure 48. the values of resistance and capacitance must be selected to provide the adequate filtering function without degrading the stand?by power by an excessive current circulation. figure 48. a small rc filter prevents the fast rising spikes from reaching the protection pin opp in presence of energetic perturbations superimposed on the input line opp + _ + ovp opp aux. winding + ntc 15 v additional filter r oppu d 1 c 1 r 1 v cc v latch r oppl
ncl30073 www. onsemi.com 22 package outline case 318g?02 issue v 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncl30073/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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